Polynomial multiplication on embedded vector architectures

High-degree, low-precision polynomial arithmetic is a fundamental computational primitive underlying structured lattice based cryptography. Its algorithmic properties and suitability for implementation on different compute platforms an active area of research, this article contributes to line work: Firstly, we present memory-efficiency performance improvements the Toom-Cook/Karatsuba multiplication strategy. Secondly, provide implementations those Arm® Cortex®-M4 CPU, as well newer Cortex-M55 processor, first M-profile core implementing Vector Extension (MVE), also known Helium™ technology. We implement Number Theoretic Transform (NTT) processor. show that despite being singleissue, in-order offering only 8 vector registers compared 32 A-profile SIMD architectures like Neon™ technology Scalable (SVE), by careful register management instruction scheduling, can obtain 3× 5× improvement over already highly optimized Cortex-M4, while maintaining low energy profile necessary use in embedded market. Finally, real-world application integrate our techniques post-quantum key-encapsulation mechanism Saber